carryout=carryin*current-stage;与门
next-stage=carryin’*current-stage+carryin*current-stage’;与门,非门,或门(或者异或门)
module(clk,current-stage,carryin,next-stage,carryout);
inputclk, current-stage,carryin;
outputnext-stage,carryout;
always@(posedgeclk)
carryout<=carryin¤t-stage;
nextstage<=